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L9230
SPI CONTROLLED H-BRIDGE
PRELIMINARY DATA
s s s s s s s s s s s s s
OPERATING SUPPLY VOLTAGE 5V TO 28V TYPICAL RDSon = 150 m FOR EACH OUTPUT TRANSISTOR (AT 25C) CONTINOUS DC LOAD CURRENT 5A (Tcase < 100 C) OUTPUT CURRENT LIMITATION AT TYP. 6A SHORT CIRCUIT SHUT DOWN FOR OUTPUT CURRENTS OVER 8A LOGIC- INPUTS TTL/CMOS-COMPATIBLE OPERATING-FREQUENCY UP TO 30 kHz OVER TEMPERATURE PROTECTION SHORT CIRCUIT PROTECTION UNDERVOLTAGE DISABLE FUNCTION DIAGNOSTIC BY SPI OR STATUS-FLAG (CONFIGURABLE) ENABLE AND DISABLE INPUT SO20 POWER PACKAGE
PowerSO20
BARE-DIE
ORDERING NUMBERS: L9230 L9230-DIE1
The H-Bridge is protected against over temperature and short circuits and has an under voltage lockout for all the supply voltages "VS" (Main DC power supply). All malfunctions cause the output stages to go tristate. The H-Bridge contains integrated free-wheel diodes. In case of free-wheeling condition, the lowside transistor is switched on in parallel of its diode to reduce the current injected into the substrate. Switching in parallel is only allowed, if the voltagelevel of the according output-stage is below the ground-level.In this case it must be ensured, that the upper transistor is switched off.
DESCRIPTION The L9230 is an SPI controlled H-Bridge, designed for the control of DC and stepper motors in safety critical applications and under extreme environmental conditions. BLOCK DIAGRAM
VS UNDERVOLTAGE VS INTERNAL 5V SUPPLY
IN1 IN2 GATE CONTROL 1 GATE CONTROL 2 LOGIC DMS SF/SCK SS SI SO MAXIMUM CURRENT LIMITATION GND
D01AT470A
OVERCURRENT HIGH-SIDE OUT1
DI EN
OUT2 OVER TEMPERATURE OVERCURRENT LOW-SIDE
March 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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L9230
PIN FUNCTION
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin GND SCK/SF IN1 VS VS OU1 OU1 SO SI GND GND DMS EN OU2 OU2 VS SS DI IN2 GND Ground SPI-Clock/Status-flag Input 1 Supply voltage Supply voltage Output 1 Output 1 serial out serial in Ground Ground Diagnostic-Mode selection (+ Supply Voltage for SPI-Interface) Enable Output 2 Output 2 Supply voltage Slave select Disable Input 2 Ground Description
PIN CONNECTION (Top view)
GND SCK IN1 VS VS OU1 OU1 SO SI GND
1 2 3 4 5 6 7 8 9 10
D01AT471
20 19 18 17 16 15 14 13 12 11
GND IN2 DI SS VS OU2 OU2 EN DMS GND
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L9230
ABSOLUTE MAXIMUM RATINGS The integrated circuit must not be destroyed by use at the limit values. Each limit value can be used, as long as no other limit is violated. Voltage reference point: All values are, if not otherwise stated, relative to ground. Direction of current flow: Current flow into a pin is positive. Rise-, fall- and delaytimes: If not otherwise stated, all rise times are between 10% and 90%, fall times between 90% and 10% and delay times at 50% of the relevant steps.
Symbol VS Parameter Supply voltage Test Condition static destruction proof dynamic destruction proof t <0.5s (single pulse, Tj < 85C) VLI ILI VLO Logic inputs IN1, IN2, DI, EN, SS, SI, SCK,DMS Logic inputs IN1, IN2, DI, EN, SS, SI, SCK,DMS Logic outputs SF, SO R 10k -0.5 Min. -1 -2 -0.5 Typ. Max. 40 40 7 -20 7 Unit V V V mA V
THERMAL DATA
Symbol Tj Tstg Tamb Rth j-case Tj_sd Parameter Junction temperature dynamic t < 1 s Storage temperature Ambient temperature Thermal resistance junction to case (2) Thermal Shutdown Junction Temperature Threshold 165 175 -55 -40 Test Condition Min. -40 Typ. Max. +150 +175 +125 +125 3 Unit C C C C C/W C
ELECTRICAL CHARACTERISTCS ( Tj = -40 to +150C; VS = 5 to 28V)
Symbol Power Supply VS Supply Voltage Static Condition Dynamic Condition (t < 500ms) Undervoltage Shutdown Switch OFF voltage Switch ON voltage Hysteresis IS Supply current f = 0 kHz, IO = 0 A f = 20kHz, IO = 0 A (at least down to 2.5V) (1) 4.7 4.5 4.7 200 13 30 5 28 40 5 5 5 V V V V V mV mA mA Parameter Test Condition Min. Typ. Max. Unit
Note: 1. For supply voltages down to 2.5V the output stages are in tristate condition and the status flag is set to low. Below 2.5V the device operates in undefined condition 2. Guaranteed by design and package characterization
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L9230
ELECTRICAL CHARACTERISTCS ( Tj = -40 to +150C; VS = 5 to 28V) (continued)
Symbol Logic inputs VI II IEN tdt Logic Input Voltage IN1, IN2, DI, EN Logic Input Current IN1, IN2, DI Input Current EN Detection Time EN, DI VI 1V VIEN 2V 1 -200 1.5 -125 75 3 100 4 2 V A A s Parameter Test Condition Min. Typ. Max. Unit
Power Outputs (OUT1, OUT2) RS Switch on Resistance LS Switch on Resistance HS Current Limitation ROUT-Vs, VS > 5 V ROUT-GND, VS > 5 V Peak value controlled inductive load L = 0,8 to 5 mH resistive load R = 0,8 to 1.8 -40 C < Tj < 165 C Tj < 175 C 5.5 6 2.5 17 11.5 1.5 7.7 A A s s 150 150 250 250 m m
|IOU|max |IOU|max ta tb ta/tb |IOUK| |IOUK| t
Switch-off Current
Switch-off time (2) Blanking time (2) Tracking (2) Short circuit detection current (1) Short Circuit Current Trecking (1) Reactivation time after internal shut down (2) Leakage Current Overcurrent- or overtemperature shut down to reactivation of the output stage Output stage switched off see figure 1
12 8 1.4 5.5
22 15 1.6 11
A mA
1600 1
ms
IL VFD trr
1 2 100
mA V ns
Free-wheel diode forward voltage IO = 3A, VS = 0V Free-wheel diode reverse recovery time (2) Outputhigh" (SF not set) (*) Switch OFF Current VS = 5V, RPull_up = 27K Tj = -40 to 165C Tj = < 175C 4.1 6 2.5
VSFHigh |Iou| max
V A A 20 A A A A
ISF ISF
Outputhigh" (SF not set) (2) Outputlow" (SF set) (3 )
VSF = 5V VSF = 1V VSF = 0.5V VSF = 0.8V 300 100 500
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L9230
ELECTRICAL CHARACTERISTCS ( Tj = -40 to +150C; VS = 5 to 28V) (continued)
Symbol Timing f fS tdon tdoff tr, tf PWM Frequency Switching Frequency during current limitation Output ON-delay Output OFF-delay Output rise-, fall Time OUT1H--> OUT1L, OUT2H--> OUT2L, IOUT = 3 A OUT1L--> OUT1H, OUT2L--> OUT2H DIn --> OUTn, En --> OUTn VS = on --> output stage active 5 4,5V < VDMS < 5,5V - IVs < 3A I for ISI, ISO, ISS, ISCK, IIN1, IIN2, IEN,IDI 0.2 IN1 --> OUT1 or IN2 --> OUT2 min. operating time 10s 2 5 3 3 0.4 30 30 5 5 1 kHz kHz s s s Parameter Test Condition Min. Typ. Max. Unit
tddis tdp
Disable Delay Time Power on Delay Time Delay time for fault detection
3
4 15 15 100
s ms s A
|I|
Effect of reverse current at power supply
(*) For lower pull up resistances than 27k the specified value of xxxV (minimum) is guaranteed by design Note: 1. In case of SC OUTx to Vs the switch off current is always higher than the start value of current regulation (|IOUK| = |IOUK| - |IOUmax| 2. Guaranteed by design 3. Value is tested down to 6V. For supply voltage below 6V on increased current can be fed back in the device via a protection path
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L9230
Figure 1. Output delay time
INn
50%
50%
tdon OUTn 90%
tdoff 10%
D01AT472
Figure 2. Disable delay time
DIn
50%
tddis OUTn 10% Z
D01AT473
Figure 3. Output switching time
90%
90%
OUTn
10% tf tr
D01AT474
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L9230
Figure 4.
LOAD CURRENT >8A CURRENT LIMITATION OVERCURRENT
typ 6.6A
A
CONTROL SIGNAL
STATUS FLAG
OVERCURRENT DETECTION DETAIL A 6.6A ta tb
ta = SWITCH_OFF TIME IN CURRENT LIMITATION tb = CURRENT LIMITATION BLANKING TIME
D01AT475
Figure 5.
Temperature-depending current-limitation Maximum rating for junction temperature Overtemperature switch-off Switch-off current in case of current limitation For 165C < Tj < 175C the maximum current decreases from
for < 1s 175C > 175C 6,6A 1,1A Tj < 165C Imax. = 6,6A 1,1A to Imax. = 2,5A 1,1A.
Tolerance-range of temperature-dependent current-reduction
Imax
6.6A
Range of Overtemperature switch-off
2.5A
165C
175C
Tj
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L9230
ELECTRICAL CHARACTERISTICS (continued) SPI INTERFACE The timing of L9230 is defined as follows: - The change at output (SO) is forced by the rising edge of the SCK signal. - The input signal (SI) is taken over on the falling edge of the SCK signal. - SS = active without any clocks at SCK is not allowed - The data received during a writing access is taken over into the internal registers on the rising edge of the SS signal, if exactly 16 SPI clocks have been counted during SS = active.
Figure 6.
10 9
SS
11
2
1
3
8
SCK
12
4
7
SO
tristate
Bit (n-3)
Bit (n-4)...1
Bit 0; LSB
5
6
SI
MSB IN Bit (n-2) Bit (n-3)
Bit (n-4)...1 LSB IN
n = 16
ELECTRICAL CHARACTERISTCS ( continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
Input SCK (SPI clock input 4.5V < DMS < 5.5V)
VSCKL VSCKH
Low Level High Level Hysteresis Input Capacity 2 0.1
1
V V
VSCK
CSCK
0.4 10
V pF
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L9230
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit A
-ISCK
Input Current
Pull up current source connected to VS
20
50
Input SS (Slave select signal)
VSSL VSSH
VSS
Low Level High Level Hysteresis Input Capacity Input Current
L9230 is selected 2 0.1
1
V V
0.4 10
V pF
A
CSS -ISS
Pull up current source connected to VDD
20
50
Input SI (SPI data input)
VSIL VSIH
VSI
Low Level High Level Hysteresis Input Capacity Input Current Pull up current source connected to VDD 20 2 0.1
1
V V
0.4 10 50
V pF
A
CSI -ISI
Output SO (Tristate output of the L9230 (SPI output); On active reset (DI) output SO is in tristate.)
VSOL VSOH CSO ISO
Low Level High Level
ISO = 2mA ISO = -2mA Capacity of the pin in tristate In tristate -10 VVDD - 0.75
0.4
V V
Capacity Leakage Current
10 10
pF
A
Input DMS (Supply-Input for the SPI-Inteface and Selection Pin for SPI- or SF-Mode)
Vi Ic
Timing
Input Voltage Input Current
SPI-Mode Status-Flag-Mode SPI-Mode
3.5 0.8 10
V V mA
t cyc t lead t lag
Cycle-Time (referred to master) Enable Lead Time (referred to master) Enable Lag Time (referred to master)
200 100 150
ns ns ns
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L9230
Symbol Parameter Test Condition Min. Typ. Max. Unit
tv
Data Valid CL = 40pF Data Valid CL = 200pF (referred to L9230) Data Setup Time (referred to master) Data Hold Time (referred to master) Disable Time (referred to L9230) Transfer Delay (referred to master) Serial clock high time (referred to master) Access time (referred to master) Clock inactive before chipselect becomes valid Clock inactive after chipselect becomes valid 150 50 8.35 200 200 Load on SO 50pF 20 50 20
40 150
ns ns ns ns
t su th t dis t dt t SCKH t SCKL
100
ns ns
s
ns ns ns ns
t rs
rise-, fall time
DIAGNOSTIC Diagnostic Threshold (Open Load Detection DMS > 4,5V, EN < 0,8V)
VOUT1 VOUT2 VOUT1 VOUT2 IOUT2 -IOUT1
Diagnostic Current
Load is available
0.8 0.8 1 VS 0.8 1000 1500 1.5 1300 2000 1.6 100
V V V V
A A
Load is missing
DMS > 4.5V, EN < 0.8V DMS > 4.5V, EN < 0.8V IOUT1 / IOUT2
700 1000 1.4 30
Tracking Diagnostic Current
tD
Delay Time
ms
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L9230
TRUTH TABLE
Pos. DI EN IN1 IN2 OUT1 OUT2 SF 3) SPI 4) DIA_REG
1. forward 2. reverse 3. Free-wheeling low 4. Free-wheeling high 5. Disable 6. Enable 7. IN1 disconnected 8. IN2 disconnected 9. DI disconnected 10. EN disconnected 11. Current limit. active 12. Undervoltage 1.) 13. Overtemperature 2.) 14. Overcurrent 2.)
L L L L H X L L Z X L X X X
H H H H X L H H X Z H X X X
H L L H X X Z X X X X X X X
L H L H X X X Z X X X X X X
H L L H Z Z H X Z Z Z Z Z Z
L H L H Z Z X H Z Z Z Z Z Z
H H H H L L H H L L H L L L
See Page 17
1.) 2.)
In case of undervoltage tristate and status-flag are reset automatically. Whenever overcurrent or overtemperature is detected, the fault is stored (i.e. status-flag remains low). The tristate conditions and the status-flag 3) are reset via DI or EN. L = Low H = High X = High or Low Z = High impedance (all output stage transistors are switched off in static state. For more inform. see next page ) Overcurrent: Overtemperature: Undervoltage: IOUT1,2 Tj VVs-GND >8,0 A >175C <5.0 V (at least down to 2,5V)
3.) 4.)
If Mode Status-Flag" is selected (see 1.5) If Mode SPI-Diagnosis is selected (see 1.5)
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L9230
Description of the state Z" The state Z" has, depending on the previous operating condition different meaning. 1. dynamical I. e. the inductive load is current carrying and is switched off according to Pos. 5, 6, 9, 10, 11, 12, 13, or 14 of the truth table a.) All output stage transistors are switched off. b.) The current flow is continued via the free wheeling diodes. c.) Free wheeling is detected by a negative voltage-level at OUn. d.) Switch on of the parallel-transistor of the current carrying diode. f.) Free wheeling is finshed, if the voltage-level on OUn is positive again. 2. statical g.) all output-stages switched off. Figure 7.
CURRENT CARRYNG IVS -IGND
FREE WHEELING
HIGH IMPEDANCE
ILOAD
VOUn VSVS-VDS
Z -VS
Z
D01AT478
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L9230
DIAGNOSTIC The Diagnosis-Mode can be selected between SPI-Diagnosis and Status-Flag Diagnosis. The choise of the Diagnosis-Mode is selected by the voltage-level on pin 12 (DMS Diagnosis Mode Selection). DMS = GND DMS = Vcc Status-Flag SPI-Diagnostic
For the connection of pins SI, SO, SS and SCK/SF see Fig. 10 respectively Fig. 11. Status-Flag The Status-Flag showes the condition tristate". At the following fault-cases the output-stages switches in tristate and set the status-flag from high to low. - Short circuit of OUT1 or OUT2 against VS or GND - Short circuit between OUT1 and OUT2 - Overcurrent - Overtemperature - Undervoltage on VS In cause of short circuit or overcurrent, the fault will be stored. The output stage switches in tristate and the status-flag is set from high level to low-level if the specified value is exceeded. If the voltage level changes from high to low on DI or from low to high on EN, the output stage switches on again and the status-flag is reset to high-level. In cause of overtemperature the fault will be stored. The output stage switches in tristate and the status-flag is set from high level to low-level if the specified value is exceeded. the voltage level changes from high to low on DI or from low to high on EN, the output stage switches on again and the status-flag is reset to high-level. In cause of undervoltage on VBatt the output stage switches in tristate and the status-flag is set from high level to low-level if the specified value is fallen. If the voltage has risen about the specified value again, the output stage switches on again and the status-flag is reset to high-level. The maximum current which can flow under normal operating conditions is limited to typical Imax. = 6,6A . When the maximum current value is reached, the output stages are switched tristate for a fixed time. According to the time-constant the current decreases exponentially until the next switch-on occurs. At the end if the fixed time the output stage switches on again and the status-flag is reset to high-level.
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L9230
SPI-INTERFACE General Discription The serial SPI interface establishes a communication link between L9230 and the systems microcontroller. L9230 always operates in slave mode whereas the controller provides the master function. The maximum baud rate is 2 MBaud (200pF). Applying an active slave select signal at SS L9230 is selected by the SPI master. SI is the data input (Slave In), SO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI clock is provided by the master. In case of inactive slave select signal (High) the data output SO goes into tristate. Figure 8.
DMS
SPI Power Supply
SS
SPI Control:
State Machine Clock Counter Control Bits Parity Generator
SI
Shift Register
DIA_REG
Depending on the application the first two bits of an instruction may be used to estabish an extended device-addressing. This gives the opportunity to operate up to 4 Slave-devices sharing one common SS signal from the Master-Unit Power Supply of the SPI-Interface SPI-Logic and I/O-Pins are alternativ supplied from DMS or Vcc internal, depending on which voltage is higher. That is why diagnosis of the EN-/DI-Pins is always possible, even in case of missing H-Bridge-power supply e.g. during Vorlauf/Nauchlauf".
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L9230
Characteristics of the SPI Interface 1) When DMS is > 3,5V, the SPI is active, independent of the state of EN or DI and the voltage on VS. During active reset conditions (DMS < 3,5V) the SPI is driven into its default state. When reset becomes inactive, the state machine enters into a waitstate for the next instruction. 2) If the slave select signal at SS is inactive (high), the state machine is forced to enter the waitstate, i.e. the state machine waits for the following instruction. 3) During active (low) state of the select signal SS the falling edge of the serial clock signal SCK will be used to latch the input data at SI. Output data at SO are driven with the rising edge of SCK. Further processing of the data according to the instruction ( i.e. modification of internal registers) will be triggered by the rising edge of the SS signal. (-> See Note) 3 ) Chipaddress: In order to establish the option of extended addressing the uppermost two bits of the instruction-byte ( i.e the first two SI-bits of a Frame ) are reserved to send a chipaddress. To avoid a busconflict the output SO must stay high impedant during the addressing phase of a frame (i.e. until the addressbits are recognised as valid chipaddress). This tristate behavior should be realised in any case, regardless wether the extended addressoption is used or not. If the chipaddress does not match, the according access will be ignored and SO remains high impedant for the complete frame regardless which frametype is applied. 5) Check byte: Simultaneously to the receipt of an SPI instruction L9230 transmitts a check byte via the output SO to the controller. This byte indicates regular or irregular operation of the SPI. It contains an initial bitpattern and a flag indicating an invalid instruction of the previous access. 6) 7) On the read access the databits at the SPI input SI are rejected. Invalid instruction/access: An instruction is invalid, if one of the following conditions is fulfilled: - an unused instruction code is detected (see tables with SPI instructions). - in case the previous transmission is not completed in terms of internal data processing. ( Violation of the minimum Access-Time. ) If an invalid instruction is detected, any modifications on registers of L9230 are not allowed. In case an unused instruction code occured the databyte "ffhex" will be transmitted after having sent the check byte. In addition any access is invalid if the number of SPI clock pulses (falling edge) counted during active SS differs from exactly 16 clock pulses (-> See Note).
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L9230
SPI Communication Figure 9. Reading access / 8 bit
SS
SI
SPI INSTRUCTION MSB
XXXX XXXX
SO
VERIFICATION BYTE MSB
DATA/8 BIT MSB
D01AT480
SPI Instruction The uppermost 2 bit of the instruction byte contains the chipadress. The individual chipadress is a mask-option and must be defined in accordance to the SPI-Members sharing on SS line. SPI Instruction-Format
MSB
7 0 6 0 5 INSTR4 4 INSTR3 3 INSTR2 2 INSTR1 1 INSR0 0 INSW
Bit
7,6 5-1 0
Name
CPAD1,0 INSTR (4-0) INSW Chip Adress (has to be `0', `0') SPI instruction (encoding) Don`t care
Description
SPI Instruction-Bytes
Encoding SPI Instruction
bit 7,6 CPAD1,0 00 00 bit 5,4,3,2,1 INSTR(4...0) 00000 00001 Bit 0 0 1 read identifier read version
Description
RD_IDENT RD_VERSION
RD_DIA
00
00100 all others
1
read DIA_REG no function
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L9230
Reset of the Diagnostic Register DIA_REG On the following conditions DIA_REG is reset: - DI high - EN low - With the rising edge of the SS-signal after the SPI-Instruction RD_DIA. - When the voltage on DMS exceeds the threshold for detecting SPI-Mode. (after undervoltage condition) - Undervoltage on VS (< 5,0V) sets Bit 0 .... Bit 3 of DIA_REG to 0000. - If UB rises over about the undervoltage level, the Bits of DIA_REG are restored (when VS internal or DMS > 3,5V)
Verification byte:
MSB
7 Z 6 Z 5 1 4 0 3 1 2 0 1 1 0 TRANS_F
Bit
0 1 2 3 4 5 6 7
Name
TRANS_F
Description
Bit = 1: error detected during previous transfer Bit = 0: previous transfer was recognised as valid Fixed to High Fixed to Low Fixed to High Fixed to Low Fixed to High send as high impedance send as high impedance
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L9230
Diagnostics/Encoding of Failures Description of the SPI Registers
Register:
7 DI
(SPI Instructions: RD_DIA)
5 4 CurrLim 3 DIA21 2 DIA20 1 Dia11 0 DIA10
DIA_REG
6 OT CurrRed
State of Reset: FFH Access by Controller: Bit
0 1 2 3 4 5 6 7 Read only
Name
DIA 10 DIA 11 DIA 20 DIA 21 CurrLim CurrRed OT DI Diagnosis-Bit1 of OUT1 Diagnosis-Bit2 of OUT1 Diagnosis-Bit1 of OUT2 Diagnosis-Bit2 of OUT2
Description
is set to 0" in case of current limitation is set to 0" in case of temperature dependet current limitation is set to 0" in case of overtemperature shows the wired-or state of the Pins EN and DI
Encoding of the Diagnostic Bits of the Output-Stages OUT1 and OUT2 DIA21
0 0 1 1 0
DIA20
0 1 0 1 0
DIA11
0 0 1 1 0
DIA10
0 1 0 1 0 Short circuit over load (SCOL) Short circuit to battery on OUT1 (SCB1) Short circuit to ground on OUT1 (SCG1) No error detected on OUT1 Open load (OL) Short circuit to battery on OUT2 (SCB2) Short circuit to ground on OUT2 (SCG2) No error detected on OUT2 Undervoltage on Pin UB
Description of DIA_REG Bit7
EN
0 0 1 1
DI
0 1 0 1
DIA_REG Bit7
0 0 1 0
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L9230
Device Identifier The IC`s identifier is used for production test purposes and features plug & play functionality depending on the systems software release. It is made up on a device-number and a revision number each one read-only accessible via standardised instructions. The Device number is defines once to allow indentification of different IC-Types by software. The Revision number may be utilised to distinguish different states of hardware. The contents is divided into an upper 4 bit field reserved to define revisions correspondending to specific software releases. The lower 4 bit field is utilised to indentify the actual maskset. Both (SWR and MSR) will start with 0000b and are increased by 1 every time an according modification of the hardware is introduced. Reading the IC Identifier (SPI Instruction: RD_IDENT):
IC Identifier1 (Device ID)
7 ID7 6 ID6 5 ID5 4 ID4 3 ID3 2 ID2 1 ID1 0 ID0
Bit
7...0
Name
ID(7...0) ID-No.: 10100001
Description L9230
Reading the IC revision number (SPI Instruction: RD_VERSION):
IC's revision number
7 SWR3 6 SWR2 5 SWR1 4 SWR0 3 MSR3 2 MSR2 1 MSR1 0 MSR0
Bit
7...4 3...0
Name
SWR(3...0) MSR(3...0)
Description
Revision corresponding to Software release: 0Hex Revision corresponding to Maskset: 0Hex
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L9230
Figure 10. Application example with SPI-Interface
DMS IN1 VOLTAGE REGULATOR VCC IN2 DI C SCK SS SO SI
UB
VBATT
OUT1
POWER-ON RESET
RESET
M
OUT2
I.E. WATCH DOG P
EN
GND
D01AT481
Figure 11. Application example with Status-Flag
47K SF VBATT VOLTAGE REGULATOR VCC IN1 IN2 C DI SS SO SI
DMS
UB
OUT1
POWER-ON RESET
RESET
M
OUT2
I.E. WATCH DOG P
EN
GND
D01AT482
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L9230
Figure 12. Application examples for Overvoltage- and Reverse-Voltage Protection
Version 1 REVERSE POLARITY PROTECTION VIA MAIN RELAIS H-BRIDGE VS VS < 40V
MAIN RELAIS
IGNITION SWITCH
BATTERY
Version 2 REVERSE POLARITY PROTECTION VIA ACTIVE DIODE H-BRIDGE VS VS < 40V
BATTERY
D01AT483
ESD-SOLIDITY The connection pins of the IC have to be protected against Electrostatic Discharge ESD) by suitable integrated protection structures. The integrated circuit has to meet the demand of the Human-Body-Model" with VC = 4kV C = 100pF and R2 = 1,5k (330 for OUT1 and OUT2). Thereby any defect or destruction of the integrated circuit must not occur. The protection structures realized to reach the ESD-strength have to be coordinated. The ESD-strength has to be verified by the test circuit given as below. Figure 13.
S2 R1 (1) (2) S1 US R2
=
V
DCVOLTMETER
C
OUT
S3
D01AT484
For the Pins 4, 5, 6, 7, 14 and 15 UC = + 4kV R1 = 100k R2 = 330 C = 100pF Number of pulses each pin: 18 Frequency: 1Hz Arrangement and performance: The requirements of MIL883D Methode 3015 have to be fulfilled.
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L9230
ISO-PULSES In the main-power-supply-system disturbance transients according to ISO 7637-1 First Edition 1990-06-01 may occur. By means of external components (see Fig. 12) the following maximum ratings of the IC will not be exceeded. statical dynamical for t < 500 ms APPENDIX A
OUT1
Load available Open Load SC -> GND on OUT1 with Load SC -> GND on OUT2 with Load SC -> UB on OUT1 with Load SC -> UB on OUT2 with Load SC -> GND on OUT1 Open Load SC -> GND on OUT2 Open Load SC -> UB on OUT1 Open Load SC -> UB on OUT2 Open Load 1 1 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 0 0 1 SC detected on normal operation SC detected on normal operation SC detected on normal operation SC detected on normal operation OL not detected OL detected OL detected OL not detected Double Fault Double Fault
-1V ...... +40V -2V ...... +40V
OUT2
Figure 14.
VBatt
int 5V IN1 1.5 mA IN2
OUT1
OUT2
1 mA
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L9230
APPENDIX B Figure 15. Voltage Supply of SPI-Logic and EN/DI-Logic
VBatt
EN DI
EN/DILogic
OutputStage
internal Vcc
DMS
Status EN/DI
DMS = GND EN/DI-Logic is supplied from internal VCC DMS = VCC EN/DI-Logic is supplied from DMS (OR int. VCC)
SO SI SCK SS
SPILogic
Undervoltage on VBatt Failure and Status Output Stage
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L9230
mm MIN. 0.1 0 0.4 0.23 15.8 9.4 13.9 1.27 11.43 10.9 5.8 0 15.5 0.8 11.1 2.9 6.2 0.1 15.9 1.1 1.1 0.031 8 (typ.) 8 (max.) 10 0.394 0.228 0.000 0.610 0.429 TYP. MAX. 3.6 0.3 3.3 0.1 0.53 0.32 16 9.8 14.5 0.000 0.016 0.009 0.622 0.370 0.547 0.050 0.450 0.437 0.114 0.244 0.004 0.626 0.043 0.043 JEDEC MO-166 0.004 MIN. inch TYP. MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570
Weight: 1.9gr
DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 G H h L N S T
OUTLINE AND MECHANICAL DATA
(1) "D and E1" do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006") - Critical dimensions: "E", "G" and "a3".
PowerSO20
N
N a2 b e A
R
c DETAIL B a1 E DETAIL A
DETAIL A e3 H
lead
D a3 DETAIL B
20 11
Gage Plane 0.35
slug
-C-
S E2 T E1 BOTTOM VIEW
L
SEATING PLANE G C
(COPLANARITY)
E3
1 10
24/25
h x 45
PSO20MEC
D1
0056635
L9230
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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